A simple dI/dt confusion, Anyone like to try & solve it ?

[Sanjay kumar]

According to calculation : -
1uH coil is giving me 50A/uS for 100uS,
If I use 4uH coil, it will give me 12.5A/uS for 400uS

What I am trying to ask specifically is : -
Will total time get increased by 4x ?
Or It will only take extra 4uS for current to reach 50A, then for the rest of the time - 100uS, It will continue at 50A ????

"It will continue at 50A"
By this I meant, 50A constant current flow for the rest 100uS.
Not rising 50A/uS.

 

[pc1966]

The thing about simulations that you always have to remember is this:

• If it tells you it won't work, it won't work.
• If it tells you it works, it might work.

In the second case it will work so long as the models used are sufficiently close to the actual components it is built with. The problem here is most manufacturers of SCR, etc, expect them to be used for controlling 50/60Hz power systems, and probably not for high energy pulse discharge, so it is unlikely the model of the SCR is accurate when pushed to extreme values of I and dI/dt.

In some cases you can "read" the SPICE model of a part as it is really a sub-circuit and just a text file you can open. Then you can see how they implemented it as a mixture of basic semiconductor models and added R/C/L to model the real part's packaging, etc.

In the example circuit above the storage capacitor is models as a pure capacitance, in reality it will have some series R & L anyway. Also every part has a blow-up point in surge current, so if you are doing this sort of stuff and want to have more than one bite of the cake you need to check the dV/dt rating of the capacitor as well (which is really a peak-current specification as I = C * dV/dt).

 

[Julie.]

The thing about simulations that you always have to remember is this:

• If it tells you it won't work, it won't work.
• If it tells you it works, it might work.

In the second case it will work so long as the models used are sufficiently close to the actual components it is built with. The problem here is most manufacturers of SCR, etc, expect them to be used for controlling 50/60Hz power systems, and probably not for high energy pulse discharge, so it is unlikely the model of the SCR is accurate when pushed to extreme values of I and dI/dt.

In some cases you can "read" the SPICE model of a part as it is really a sub-circuit and just a text file you can open. Then you can see how they implemented it as a mixture of basic semiconductor models and added R/C/L to model the real part's packaging, etc.

In the example circuit above the storage capacitor is models as a pure capacitance, in reality it will have some series R & L anyway. Also every part has a blow-up point in surge current, so if you are doing this sort of stuff and want to have more than one bite of the cake you need to check the dV/dt rating of the capacitor as well (which is really a peak-current specification as I = C * dV/dt).

Agree, although to be fair, the spice models do allow more characteristics to be added to them than I have, series r & x, leakage r & x and so on.

But absolutely agree with the interpretation of the results, just looking at the voltage, does not give an indication of the current etc.

In the model it shows the voltage oscillating as expected, but only when you look at the current do you realise the magnitude, any current even approaching this could damage components.

Calculate the fault level on a site, again it's a guide and doesn't in itself indicate the suitability of any equipment

 

[Sanjay kumar]

The thing about simulations that you always have to remember is this:

• If it tells you it won't work, it won't work.
• If it tells you it works, it might work.

In the second case it will work so long as the models used are sufficiently close to the actual components it is built with. The problem here is most manufacturers of SCR, etc, expect them to be used for controlling 50/60Hz power systems, and probably not for high energy pulse discharge, so it is unlikely the model of the SCR is accurate when pushed to extreme values of I and dI/dt.

In some cases you can "read" the SPICE model of a part as it is really a sub-circuit and just a text file you can open. Then you can see how they implemented it as a mixture of basic semiconductor models and added R/C/L to model the real part's packaging, etc.

In the example circuit above the storage capacitor is models as a pure capacitance, in reality it will have some series R & L anyway. Also every part has a blow-up point in surge current, so if you are doing this sort of stuff and want to have more than one bite of the cake you need to check the dV/dt rating of the capacitor as well (which is really a peak-current specification as I = C * dV/dt).

Thank you for valuable information!

According to datasheet maximum peak current of single pulse is specified with 1000A per component.
I Am using 10 in parallel

 

[pc1966]

According to datasheet maximum peak current of single pulse is specified with 1000A per component.
I Am using 10 in parallel

You will need to take steps to ensure they share the current equally, so a very small R or similar for each to make that happen (that could be 10 equal moderate lengths of medium-size wire from capacitors to load/switching point).

Also if one capacitor fails the other 9 will dump their energy in to the failed one. I would recommend a metal box to contain any fragments or flames...

 

[DPG]

I think he means 10 x SCRs in parallel. I'm a bit out of touch, but don't you need to use some low value 'balancing' resistors?

 

[Sanjay kumar]

You will need to take steps to ensure they share the current equally, so a very small R or similar for each to make that happen (that could be 10 equal moderate lengths of medium-size wire from capacitors to load/switching point).

Also if one capacitor fails the other 9 will dump their energy in to the failed one. I would recommend a metal box to contain any fragments or flames...

I am very far from actually running this circuit, But yes I will take necessary precautions mentioned by you.
More importantly, I will give this work to a professional E.E who lives near me to do this experiment.
Thank you!
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I think he means 10 x SCRs in parallel. I'm a bit out of touch, but don't you need to use some low value 'balancing' resistors?

No, I meant 10 capacitors in parallel
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I think he means 10 x SCRs in parallel. I'm a bit out of touch, but don't you need to use some low value 'balancing' resistors?

& about the resistor, I hope Someone from here can help me with choosing that ??

 

[pc1966]

I think he means 10 x SCRs in parallel. I'm a bit out of touch, but don't you need to use some low value 'balancing' resistors?

For parallel SCR or transistors - absolutely! As they heat the volt drop decreases, so one will end up hogging all of the current and being destroyed. So at the normal working current you would want some small R in series with each semiconductor device dropping around 0.1V or so to ensure they remain fairly evenly balanced.

MOSFET go the other way, they reduce conduction as they heat so tend to be self-equalising.
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For the parallel C you need to allow some impedance (R and/or L) per-capacitor that drops, say, around 5% of the discharge voltage at peak current so they are broadly balanced.

 

[Sanjay kumar]

For the parallel C you need to allow some impedance (R and/or L) per-capacitor that drops, say, around 5% of the discharge voltage at peak current so they are broadly balanced.

How to do that ??
Maybe wire resistance will be enough ??

Although, I was thinking of putting those capacitors on copper busbar.

 

[pc1966]

How to do that ??

Start with series R that is 10 * (peak V) / (peak I) and simulate (using 10 capacitors, etc) it to see what the drop is on each balancing resistor. Adjust R up or down as needed.

Some versions of SPICE allow you to specify a tolerance of parts then you can run a Monte Carlo simulation to see the spread of results.

 

[Sanjay kumar]

Start with series R that is 10 * (peak V) / (peak I) and simulate (using 10 capacitors, etc) it to see what the drop is on each balancing resistor. Adjust R up or down as needed.

Some versions of SPICE allow you to specify a tolerance of parts then you can run a Monte Carlo simulation to see the spread of results.

Although, I was thinking of putting those capacitors on copper busbar.
But Maybe wire resistance will be help ??

Should I use busbar?

 

[DPG]

Although, I was thinking of putting those capacitors on copper busbar.
But Maybe wire resistance will be help ??

Should I use busbar?

Sturdy copper sounds better. Although if you use a suitable size wire then resistance shouldn't be a problem.

 

[pc1966]

I should have said "R that is 0.05 * 10 * (peak V) / (peak I)"

You can use a busbar but unless you can ensure the capacitors are equal then you have the current-sharing problem (and issues of one end of busbar being the load). You could use small ohm resistors between each cap and the bar (probably of the order of 0.1 to 0.5 ohms each) but they have to be very high surge capable types. Some inductance might help, so a small coil of around 1mm diam resistance wire might do.

Simulate. Measure. Repeat until it works!
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Also to add that for testing the current-share you can do that at, say, 5V to avoid blowing anything up. That way you can safely put a scope on the various R & C to verify how well it is sharing.

Also if you have, say, 12 capacitors and a LCR meter you can select the 10 best-matching, etc. to be used.

If you do go down the busbar route then take one output off the end of one bar, and the other output off the opposite end of the other bar - that way each C has roughly the same distance to the load.

 

[Sanjay kumar]

If you do go down the busbar route then take one output off the end of one bar, and the other output off the opposite end of the other bar - that way each C has roughly the same distance to the load.

Hmm.... This is interesting!
I do have LCR meter

 

[HappyHippyDad]

Ok, bit of a further reply, I thought it would be worth posting here as it does illustrate why we need ALL the information rather than snippets because it can change the question completely.

Basically the idea is to discharge a capacitor with 945V stored via an inductor.

In this case – pictured here

View attachment 61188

It is not a simple constant voltage step change, the capacitor will have a store of energy, as the switch is closed it will discharge into the coil, this would produce a back emf – this interaction between the decay of voltage from the capacitor and growth of current through the inductor “fight against each other” – a bit like dropping a weight on a spring – the weight will fall then the spring will pull it back, then the weight will fall etc – basically discharging a capacitor into an inductor will oscillate!

Rather than just L di/dt the equation becomes:

View attachment 61190


Which is a second order differential equation – hence the oscillation.

There are a number of shortcuts to solving this, depending on the relative values of C, L & R – as here:

View attachment 61189


So forcing a low resistance will cause a decaying oscillation, but increasing the resistance beyond 2 Sqrt (L/C) will cause a non-oscillatory decay!





If I was solving this for the generic solution, I would use laplace transforms to solve the differential equation as a set of linear equations, I may do this later if the football is rubbish!

Probably the easiest solution these days is to download a program such as LTSpice – it’s free and allows time domain modelling of any circuit – not just L & C, but actually any SCR you may wish to use as the switching device.

This requires little mathematical knowledge.

Your 'bit' of a further reply is a rather impressive 'bit'.

 

[Julie.]

Your 'bit' of a further reply is a rather impressive 'bit'.

Not really, just a bit of circuit theory an a bit of maffs, goes intas, takes aways an stuff!