7u
With the 93 at 0000 please measure the voltage of the output of the AND with reference to OV. It has to be less than 0.8V to be interpreted as a logic 0 by the 93. Do this with nand connected to the and output and then with nand disconnected from the and output.
if R1 is not being held at a voltage which 93 interprets as a 0, but rather as a 1 then all it takes to reset 93 is for R2 to become logic 1 which happens when qd becomes 1 at a count of 0100. Thus it resets to 0000.
For 74LS a logic 1 input is a voltage greater than 2V.
Have you tried this? That cmos AND should be able to drive one 74LS input in your case R1. The Qd connects to R2.
With the 93 at 0000 please measure the voltage of the output of the AND with reference to OV. It has to be less than 0.8V to be interpreted as a logic 0 by the 93. Do this with nand connected to the and output and then with nand disconnected from the and output.
if R1 is not being held at a voltage which 93 interprets as a 0, but rather as a 1 then all it takes to reset 93 is for R2 to become logic 1 which happens when qd becomes 1 at a count of 0100. Thus it resets to 0000.
For 74LS a logic 1 input is a voltage greater than 2V.
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You could do those voltage measurements I suggested recently. You could do the trial without the NAND in circuit.
Please measure the voltage of your power supply using a voltmeter and tell me what it is. Not the meter on the power supply.
_q12x_
DIY
The voltage of the output of the AND when 93 is at 0b0000 (0decinal) is 0.025V = 25mV
The voltage of the output of the AND when 93 is at 0b0011 (3decinal) is 5V
so when is reaching 4decimal , is already High?
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The discrete diode AND gate will not work because when its inputs are connected to 0V, the output does not become 0V ie logic 0. If you study my diagram you will see that the output of CMOS is like a switch and the two resistors. When the output is logic 0 a current will flow creating a voltage drop Vx and there will be the forward voltage Vf = 0.7V across the silicon diode. Thus Vo = Vx + Vf = Vx + 0.7. For TTL 74LS the maximum voltage which will interpreted as a logic must be less than 0.8V. You can see then that this circuit cannot produce a logic 0 when both inputs either or both inputs are logic 0 - the output will always be greater than 0.8V. It might work if you used germanium diodes which have a Vf of 0.2V. But see my later post about using two 7400 NAND gates.
PS: You also have an output pin loading problem because you drive the LEDs directly from them. This will disturb the voltages at their output in logic state 1 since you turn on the LEDs then. Better practice is to drive each LED via a buffer gate. The buffer gate and LED circuit I use is in the second attachment. I wire the LED like this from the 5V rail because generally logic gates can 'sink' more current to the 0V rail than they can 'source' current from the 5V rail. I leave you to look up the terms sink and source.
Attachments
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_q12x_
DIY
I told you, this 7493 counter needs something 'special' on its R01. As you remember from my previeous videos, if I give it a direct metal wire link to other pins, it is working without any issues. Im thinking maybe the voltage is too low, being absorbed by the AND gate and not enough to drive the pin of the counter....Im thinking a transistor to buffer up the voltage?
Please see video of your circuit slightly modified counting states 0 to 6 and then resetting and repeating. It is important that Ro1 and Ro2 go high and low at exactly the same time so that all four ff are reset to 0 at the same time too.You may find two 2 input CMOS AND gates or the 3 input diode circuit will do what my 4 NANDS do below - to AND together Qa, Qb and Qc.
Note well please that the far right gate is a NAND - I missed off its small circle on the output.
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_q12x_
DIY
yes, indeed it is counting to 7, 6 visible but 7 resets to 0 but is still a 7.
if you start counting from 0 to 6, you get 7 counts.
ok so 4 NAND Gates. Got it.
Glad that you made it work !!!! I was out of any ideas.
Will see if it will work on mine now.
Let me try it quickly in the simulator first to confirm it.
then I will get into real thing.
The 4 Nand gates are used to make two 2 input And gates. If you study the circuit you can see how first Qa and Qb are combined by And. The output of this And is an input to the second And gate along with Qc. The second and gate produces a logic 1 when Qa, Qb and Qc are all logic 1 to send a reset pulse to R1 and R2.
Why it matters to connect R1 and R2 together is because we have to ensure that the reset inputs go to logic 1 and logic 0 at exactly the same time. There is actually rather more technical detail but forgive me for saying it would not be easily understood by you now. Just to mention that propagation delays, assertion and de-assertion durations for the reset signals, reset recovery times, meta-stable states of the flip flops and the timing of state changes including of the clocks ClkA and ClkB come into play. Things happen very quickly inside the 7493 but not instantaneously - there is sequencing of internal state changes which take a finite time to complete and are ensured by the modifications I have shown you.
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_q12x_
DIY
From that entire explanation, what is trully important to me and actually explains a behaviour, a cause and effect if you will, is ONLY this proposition. Try to concentrate on this kind of explanation at least with me. To advance faster and further !!! Its our only goal, right?
_q12x_
DIY
This was hardcore to me - simply because this is my first time using and understanding and working with logic gates and the other NEW IC's that accompanied them. I like them all so thats why I stay and work slowly to understand them. And I did, in a good percentage, in contrast to where I started, having some general idea about them, now Im sure about them because I actually worked with them. What a crazy project. I was desperate at some point because I started to doubt if I will actually manage to obtain anything on that matrix led. There were so many steps to make. I got scared I couldnt make it. But I did after some break. Im always working with numerous small breaks !!! Charge and discharge is my saying. Hard core I tell you. And it was harder for me because I had to do double the work, 1 in simulator and 2 in reality.
_q12x_
DIY
I used a 555 astable circuit running at about 1000Hz. If I wanted it to run slower I added in a larger capacitor in parallel with the one required for 1000Hz.
something like this:
Designing 555 Astables - https://learnabout-electronics.org/Oscillators/osc44.php
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