AT28C16 EEPROM learning experiments

[_q12x_]

Thanks to mister @marconi , I received his chip AT28C16 gift from England !
I will start to make the 5x7 led matrix project that you did.
I will make it alone as much as I can (as usual). And I will ask you for clarifications on the way.

 

[_q12x_]

it is that AND gate !

 

[marconi]

7u

I have to take my wife out but quickly the 4000 series output can only drive one 74LS series input. Try disconnecting the nand so the and only drives the reset input.

Have you tried this? That cmos AND should be able to drive one 74LS input in your case R1. The Qd connects to R2.

With the 93 at 0000 please measure the voltage of the output of the AND with reference to OV. It has to be less than 0.8V to be interpreted as a logic 0 by the 93. Do this with nand connected to the and output and then with nand disconnected from the and output.

if R1 is not being held at a voltage which 93 interprets as a 0, but rather as a 1 then all it takes to reset 93 is for R2 to become logic 1 which happens when qd becomes 1 at a count of 0100. Thus it resets to 0000.

For 74LS a logic 1 input is a voltage greater than 2V.

 

[_q12x_]

A new AND Gate , a new breakthrough ! But still not good.
Now Im trully desperate. I have NO idea what to do next.
Please see this small video here and tell me what you think.

 

[marconi]

A new AND Gate , a new breakthrough ! But still not good.
Now Im trully desperate. I have NO idea what to do next.
Please see this small video here and tell me what you think.

You could do those voltage measurements I suggested recently. You could do the trial without the NAND in circuit.

Please measure the voltage of your power supply using a voltmeter and tell me what it is. Not the meter on the power supply.

 

[_q12x_]

With the 93 at 0000 please measure the voltage of the output of the AND with reference to OV. It has to be less than 0.8V to be interpreted as a logic 0 by the 93.

The voltage of the output of the AND when 93 is at 0b0000 (0decinal) is 0.025V = 25mV
The voltage of the output of the AND when 93 is at 0b0011 (3decinal) is 5V
so when is reaching 4decimal , is already High?

 

[marconi]

Now do it with And connected to 93 only and then 93 and Nand.

 

[marconi]

A new AND Gate , a new breakthrough ! But still not good.
Now Im trully desperate. I have NO idea what to do next.
Please see this small video here and tell me what you think.

 

[marconi]

Swap the cmos AND gate for the circuit shown in the attachment. This circuit makes a 2 input AND gate from two NAND gates. I think you have two TTL nand gates spare in ic J33 a 7400.

 

[marconi]

A new AND Gate , a new breakthrough ! But still not good.
Now Im trully desperate. I have NO idea what to do next.
Please see this small video here and tell me what you think.

The discrete diode AND gate will not work because when its inputs are connected to 0V, the output does not become 0V ie logic 0. If you study my diagram you will see that the output of CMOS is like a switch and the two resistors. When the output is logic 0 a current will flow creating a voltage drop Vx and there will be the forward voltage Vf = 0.7V across the silicon diode. Thus Vo = Vx + Vf = Vx + 0.7. For TTL 74LS the maximum voltage which will interpreted as a logic must be less than 0.8V. You can see then that this circuit cannot produce a logic 0 when both inputs either or both inputs are logic 0 - the output will always be greater than 0.8V. It might work if you used germanium diodes which have a Vf of 0.2V. But see my later post about using two 7400 NAND gates.

PS: You also have an output pin loading problem because you drive the LEDs directly from them. This will disturb the voltages at their output in logic state 1 since you turn on the LEDs then. Better practice is to drive each LED via a buffer gate. The buffer gate and LED circuit I use is in the second attachment. I wire the LED like this from the 5V rail because generally logic gates can 'sink' more current to the 0V rail than they can 'source' current from the 5V rail. I leave you to look up the terms sink and source.

 

[_q12x_]

Swap the cmos AND gate for the circuit shown in the attachment. This circuit makes a 2 input AND gate from two NAND gates. I think you have two TTL nand gates spare in ic J33 a 7400.

This, I can do.

 

[_q12x_]

AND Gate from 2 NAND Gates using a 7400 IC :
Very interesting results....

 

[marconi]

I will make the circuit and check.

Do all the jump leads have end to end continuity?

 

[_q12x_]

yes they do ..........................

 

[_q12x_]

I moved everything on my usual testing breadboard but the result is the same.
At least I eliminated another variable : "the breadboard".

 

[_q12x_]

Ive noticed the HIGH voltage is 3.5V when the power supply is at 5V.
I push up to 6V the power and the HIGH become 4.5V, very close to 5V.
But still no effect. I reverted to 5V as it was.