AT28C16 EEPROM learning experiments

_q12x_ · Sep 16, 2022

Thanks to mister @marconi , I received his chip AT28C16 gift from England !
I will start to make the 5x7 led matrix project that you did.
I will make it alone as much as I can (as usual). And I will ask you for clarifications on the way.

marconi · Sep 20, 2022

Now do it with And connected to 93 only and then 93 and Nand.

marconi · Sep 21, 2022

_q12x_ said:
A new AND Gate , a new breakthrough ! But still not good.
Now Im trully desperate. I have NO idea what to do next.
Please see this small video here and tell me what you think.

marconi · Sep 21, 2022

Swap the cmos AND gate for the circuit shown in the attachment. This circuit makes a 2 input AND gate from two NAND gates. I think you have two TTL nand gates spare in ic J33 a 7400.

marconi · Sep 21, 2022

_q12x_ said:
A new AND Gate , a new breakthrough ! But still not good.
Now Im trully desperate. I have NO idea what to do next.
Please see this small video here and tell me what you think.

The discrete diode AND gate will not work because when its inputs are connected to 0V, the output does not become 0V ie logic 0. If you study my diagram you will see that the output of CMOS is like a switch and the two resistors. When the output is logic 0 a current will flow creating a voltage drop Vx and there will be the forward voltage Vf = 0.7V across the silicon diode. Thus Vo = Vx + Vf = Vx + 0.7. For TTL 74LS the maximum voltage which will interpreted as a logic must be less than 0.8V. You can see then that this circuit cannot produce a logic 0 when both inputs either or both inputs are logic 0 - the output will always be greater than 0.8V. It might work if you used germanium diodes which have a Vf of 0.2V. But see my later post about using two 7400 NAND gates.

PS: You also have an output pin loading problem because you drive the LEDs directly from them. This will disturb the voltages at their output in logic state 1 since you turn on the LEDs then. Better practice is to drive each LED via a buffer gate. The buffer gate and LED circuit I use is in the second attachment. I wire the LED like this from the 5V rail because generally logic gates can 'sink' more current to the 0V rail than they can 'source' current from the 5V rail. I leave you to look up the terms sink and source.

_q12x_ · Sep 21, 2022

marconi said:
Swap the cmos AND gate for the circuit shown in the attachment. This circuit makes a 2 input AND gate from two NAND gates. I think you have two TTL nand gates spare in ic J33 a 7400.

This, I can do.

_q12x_ · Sep 21, 2022

AND Gate from 2 NAND Gates using a 7400 IC :
Very interesting results....

marconi · Sep 21, 2022

I will make the circuit and check.

Do all the jump leads have end to end continuity?

_q12x_ · Sep 21, 2022

yes they do

..........................

_q12x_ · Sep 21, 2022

I moved everything on my usual testing breadboard but the result is the same.
At least I eliminated another variable : "the breadboard".

[ElectriciansForums.net] AT28C16 EEPROM learning experiments

_q12x_ · Sep 21, 2022

Ive noticed the HIGH voltage is 3.5V when the power supply is at 5V.
I push up to 6V the power and the HIGH become 4.5V, very close to 5V.
But still no effect. I reverted to 5V as it was.

_q12x_ · Sep 21, 2022

I told you, this 7493 counter needs something 'special' on its R01. As you remember from my previeous videos, if I give it a direct metal wire link to other pins, it is working without any issues. Im thinking maybe the voltage is too low, being absorbed by the AND gate and not enough to drive the pin of the counter....Im thinking a transistor to buffer up the voltage?

_q12x_ · Sep 21, 2022

adding a transistor to the AND Gate
-now counting to 4 and resetting - like the first 4081

_q12x_ · Sep 21, 2022

I put the osciloscope on the 7493
R02 does not get high at all. Only R01 and CKB.
What is the role or what is the mechanism of R01 and R02?

marconi · Sep 21, 2022

Please see video of your circuit slightly modified counting states 0 to 6 and then resetting and repeating. It is important that Ro1 and Ro2 go high and low at exactly the same time so that all four ff are reset to 0 at the same time too.

You may find two 2 input CMOS AND gates or the 3 input diode circuit will do what my 4 NANDS do below - to AND together Qa, Qb and Qc.

Note well please that the far right gate is a NAND - I missed off its small circle on the output.

_q12x_ · Sep 21, 2022

marconi said:
counting states 0 to 6 and then resetting and repeating

yes, indeed it is counting to 7, 6 visible but 7 resets to 0 but is still a 7.
if you start counting from 0 to 6, you get 7 counts.

marconi said:
Note well please that the far right gate is a NAND - I missed off its small circle on the output.

ok so 4 NAND Gates. Got it.
Glad that you made it work !!!! I was out of any ideas.
Will see if it will work on mine now.
Let me try it quickly in the simulator first to confirm it.
then I will get into real thing.

_q12x_ · Sep 21, 2022

Ive inverted your circuit to fit my circuit:

And I simulated it already and, miracle, it works !!! (in the simulation)

Now I will try it in reality.

_q12x_ · Sep 21, 2022

YES, mister @marconi it works in reality as well.
Really, Congratulations !
I am making the movie right now and post it very soon !
What a ride... Im very happy !
Thank you.

_q12x_ · Sep 21, 2022

While at this stage... can you explain to me how you think? How is your logic about these logic gates? How did you managed to come to this circuit? The logic before making the circuit ! What you were thinking?

_q12x_ · Sep 21, 2022

Here is the video about your success mister @marconi !

marconi · Sep 22, 2022

_q12x_ said:
While at this stage... can you explain to me how you think? How is your logic about these logic gates? How did you managed to come to this circuit? The logic before making the circuit ! What you were thinking?

The 4 Nand gates are used to make two 2 input And gates. If you study the circuit you can see how first Qa and Qb are combined by And. The output of this And is an input to the second And gate along with Qc. The second and gate produces a logic 1 when Qa, Qb and Qc are all logic 1 to send a reset pulse to R1 and R2.

Why it matters to connect R1 and R2 together is because we have to ensure that the reset inputs go to logic 1 and logic 0 at exactly the same time. There is actually rather more technical detail but forgive me for saying it would not be easily understood by you now. Just to mention that propagation delays, assertion and de-assertion durations for the reset signals, reset recovery times, meta-stable states of the flip flops and the timing of state changes including of the clocks ClkA and ClkB come into play. Things happen very quickly inside the 7493 but not instantaneously - there is sequencing of internal state changes which take a finite time to complete and are ensured by the modifications I have shown you.

marconi · Sep 22, 2022

So next you are working on the 74138 circuitry?

_q12x_ · Sep 22, 2022

marconi said:
Why it matters to connect R1 and R2 together is because we have to ensure that the reset inputs go to logic 1 and logic 0 at exactly the same time.

From that entire explanation, what is trully important to me and actually explains a behaviour, a cause and effect if you will, is ONLY this proposition. Try to concentrate on this kind of explanation at least with me. To advance faster and further !!! Its our only goal, right?