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Discuss AT28C16 EEPROM learning experiments in the UK Electrical Forum area at ElectriciansForums.net
counting states 0 to 6 and then resetting and repeating
ok so 4 NAND Gates. Got it.Note well please that the far right gate is a NAND - I missed off its small circle on the output.
The 4 Nand gates are used to make two 2 input And gates. If you study the circuit you can see how first Qa and Qb are combined by And. The output of this And is an input to the second And gate along with Qc. The second and gate produces a logic 1 when Qa, Qb and Qc are all logic 1 to send a reset pulse to R1 and R2.While at this stage... can you explain to me how you think? How is your logic about these logic gates? How did you managed to come to this circuit? The logic before making the circuit ! What you were thinking?
From that entire explanation, what is trully important to me and actually explains a behaviour, a cause and effect if you will, is ONLY this proposition. Try to concentrate on this kind of explanation at least with me. To advance faster and further !!! Its our only goal, right?Why it matters to connect R1 and R2 together is because we have to ensure that the reset inputs go to logic 1 and logic 0 at exactly the same time.
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